PCBA testing: how you actually know the board works

Guide · PCBA Testing PCBA testing: how you actually know the board works A board that assembles clean is not a board that works. In-circuit test, flying probe, AOI, X-ray and functional test each find a different class of defect — and the test plan is where good and bad EMS partners quietly diverge. This guide explains what each method finds, what it costs, and the questions to ask before you commit. Why test is not optional The cost curve of a defect is the same shape as the DFM cost curve: a bad joint found at functional test costs a board; found by your customer it costs a recall. Test exists to move that find as early as possible. The discipline is to choose the right test for the risk — over-testing a simple board wastes money, under-testing a safety board is a liability. The test-strategy pyramid Think of a test plan as a pyramid, not a shopping list. The base is cheap and fast and runs on every board; the apex is expensive and targeted and runs only where the risk justifies it. Base — AOI. Cameras on every populated board, inline after reflow, catching placement and solder defects for near-zero marginal cost. Middle — electrical test. ICT or flying probe verifies each net and each component value; this is where coverage per node lives. Upper middle — X-ray. Selectively applied to BGAs, QFNs and other bottom-terminated parts that optical and electrical tests cannot fully see. Apex — functional test. Powers the board and exercises it as the product will be used; the most valuable check and the most expensive per unit. A sound plan stacks the layers so each one catches what the layer below cannot see. A board with a hidden BGA open passes AOI and can pass ICT if the open is on an unprobed pin; only X-ray or a functional check will catch it. The handoff between layers is what makes the pyramid work: AOI clears the obvious placement faults, electrical test clears the component and net faults, X-ray clears the hidden joints, and functional test clears what is left — so each downstream stage sees fewer defects, and the escapes that do reach the field are the ones no test was designed to catch. Visual and automated optical inspection (AOI) AOI uses cameras to compare the populated board against a golden reference, catching missing parts, wrong parts, tombstones, polarity and solder bridges. It is fast and cheap, and it runs inline after reflow. Its limit: it sees the surface, not under the part or inside the joint. A BGA with a hidden open passes AOI every time. How the board gets built. In-circuit test (ICT) ICT uses a bed-of-nails fixture pressing test pins onto test points to measure each component in place — resistor values, shorts, opens, and basic functionality. It is the most thorough electrical check, but it needs a fixture, which costs money and lead time and locks the board layout (test points cannot move after the fixture is cut). ICT pays for itself on stable, high-volume designs where the fixture cost is amortized across thousands of units. Flying probe Flying probe is ICT without the fixture: robotic probes move to test points programmatically. No fixture cost, fast to set up, ideal for prototypes and low volume. The trade-off is speed — a flying-probe pass is slower than a fixtured ICT, so it does not scale to high volume as cheaply. The right tool for NPI and short runs; ICT for the mature product. Where test fits in the gates. In-circuit test vs flying probe: how to choose The two electrical methods answer the same question — is each net connected, and is each part the right value — but they cost differently and scale differently. Fixture. ICT needs a bed-of-nails fixture cut to your layout; flying probe needs none, only a program. Setup. A flying-probe program is written in hours to a day and changes with the revision; an ICT fixture takes days to weeks and must be recut when the layout moves. Throughput. A fixtured ICT probes every point in one press and runs seconds per board; flying probe moves sequentially and runs slower per unit. Cost curve. ICT carries a high fixed cost (the fixture) and a low per-unit cost, so it wins on stable volume; flying probe has near-zero fixed cost and higher per-unit time, so it wins on prototypes and short runs. The practical rule: fly the board through EVT and DVT while the layout is still moving, and cut the ICT fixture at PVT when the design freezes and the volume justifies the amortization. There is also a hybrid worth knowing: run flying probe as the first-article and low-volume check, then add a fixture only when the run rate makes the fixture pay for itself — many programs never cross that line and fly the whole life of the product. X-ray inspection X-ray sees through the package to the joint underneath — the only way to verify BGAs, QFNs and other bottom-terminated parts. It finds voids, head-in-pillow and insufficient solder that AOI cannot. It is used selectively (or on every board for high-reliability programs) because it is slower and more expensive than optical inspection. For any board with hidden-pad packages, X-ray is not a luxury. Boundary scan (JTAG) Boundary scan (IEEE 1149.1) uses the test access port already built into many processors, FPGAs and other compliant devices to drive and read each pin from inside the silicon. It verifies the interconnects between compliant parts without needing physical access to the net — useful exactly where probes cannot reach, such as under a BGA or on a dense, high-layer board. The same boundary-scan mechanism is what lets modern programmable logic be configured in-system (Horowitz & Hill, The Art of Electronics, 3rd ed., p. 802). Boundary scan does not replace AOI or ICT; it complements them. It checks connectivity and can read device IDs and program flash, but it cannot measure an analog component value the way ICT can. On boards heavy with FPGA and BGA content, boundary scan is often the cheapest way to get real electrical coverage on nets a fixture cannot touch. It earns its keep only when the board has compliant devices and nets that are genuinely hard to reach: a simple two-layer board with through-hole parts and full test-point access gains nothing from it, while a dense multi-layer board with large BGA and FPGA content gains a lot. Functional test (FCT) FCT powers the board and exercises it as the product would be used — does it boot, communicate, sense, drive. This is the test that catches the defects no other method sees: a wrong-value component that still passes continuity, a firmware mismatch, a marginal signal. FCT is the last line and the most valuable, because it answers the only question the customer cares about: does it work? Burn-in and environmental stress For automotive, medical and other high-reliability programs, boards may run under elevated temperature and load for hours (burn-in) or cycle through temperature and vibration (HALT/HASS) to flush out early-life failures. This is where infant-mortality defects are caught before they reach the field. It adds cost and time, and is justified exactly when field failure is unacceptable. Functional test and burn-in, done properly A functional test is only as good as the specification it is written against. Before the harness or the fixture is built, the test engineer needs the answer to one question: what must the board do to be accepted? That answer — boot, enumerate, communicate, sense, drive, calibrate — becomes a written procedure with pass/fail limits, not a power-it-up-and-check-the-LED exercise. Burn-in is a different instrument. It runs the board under elevated temperature and load for a set number of hours to accelerate the early-life failures that follow the bathtub curve — the infant-mortality region where a marginal solder joint or a weak component dies in the first hours rather than the first year. HALT and HASS go further, cycling temperature and vibration to find and then screen for latent weaknesses. All three add time and cost, and are justified exactly when a field failure is unacceptable: automotive, medical and safety-relevant boards. Design for test: make the board testable before it is locked Test access is a layout decision, not a test-department afterthought. Three choices made during design determine how cheaply and how well a board can be tested later: Test points. Every net that matters needs a probe point or an accessible via on one side. Without them, coverage drops and the fixture gets harder and more expensive to cut. Spacing and clearance. Test pads need pitch and clearance from tall parts and board edges so a fixture or flying probe can land reliably. Hidden packages. BGAs and QFNs must have their critical nets fanned out to test points or covered by boundary scan, because optical and probe access end at the package edge. The cheapest time to add a test point is in the layout; the most expensive is after the fixture is cut and the design is in the field. A good EMS reviews test access at the DFM stage and flags what cannot be tested before you commit to a revision. A bed-of-nails fixture can carry hundreds or thousands of pins, but every pin needs a landing point on the board; leaving test points off a handful of critical nets can silently drop coverage by a wide margin, because a net that cannot be probed is a net that cannot be verified electrically. DFM for electronics, in detail. Defect coverage and first-pass yield: read the numbers carefully Two metrics get quoted loosely in PCBA and mean very different things. Node coverage is the fraction of nets an electrical test touches; fault coverage is the fraction of the realistic fault models — shorts, opens, wrong value, missing part — the test would actually catch. A fixture can probe most of a board yet still miss faults if the program only checks continuity and not component value. When a partner quotes a coverage percentage, ask which one it is and what fault model sits behind it. First-pass yield is the share of boards that pass the full test sequence the first time, without rework. It is useful only when the test sequence is held constant — loosen the test and the yield looks better while the customer sees more field failures. Watch the trend, not the headline number: a stable or rising first-pass yield at a constant test spec says the process is under control; a rising yield that coincides with a softer spec says something else. Each method owns a slice of the defect space: AOI owns placement and solder-shape faults, electrical test owns value and connectivity faults, X-ray owns hidden-joint faults, and functional test owns everything that only shows up when the board is powered and doing its job. How test ties into the quality system Test is not a filter at the end of the line; it is a sensor feeding the process. The same statistical discipline that governs machining governs assembly. The factory runs control charts on critical characteristics, and the numbers are what they are — In plain terms: Cp measures whether the process spread fits inside the tolerance; Ca measures whether the process is centered; Cpk combines both into one number. The house standard is a Cpk of at least 1.67 for critical characteristics and at least 1.33 for general ones. Why this matters to a buyer of PCBA: the same control-chart discipline should apply to the board line. Ask who owns the yield data, how often it is plotted, and what happens when a point drifts. A partner that plots first-pass yield and a defect Pareto by root cause is one that improves; a partner that reports only a pass/fail stamp is one you cannot audit. In our EMS and CNC shop, test results, process parameters, batch numbers and operator data are traced end to end, so a field return can be walked back to the shift, the reel and the machine. Building a test plan: the questions to ask What does your ICT/flying-probe coverage percentage mean? 90% node coverage is different from 90% fault coverage. Ask which. Which packages get X-ray? If the answer is “none,” and you have BGAs, walk away. What is the functional test? A real FCT exercises the product; a “power-on light” is not a functional test. Who writes the test, and who owns the yield data? A partner that owns the yield data improves; one that hides it does not. The buyer's test-plan checklist Before you commit to an EMS for a board, work down this list and get each answer in writing: What runs on every board, and what runs on sample? AOI and ICT or flying probe should be 100%; X-ray may be sampled or 100% depending on risk. Which packages get X-ray, and at what void criteria? Get the accept/reject threshold for BGA voids in writing. What is the functional test, and who writes it? Ask for the procedure and the pass/fail limits, not a photo of a lit board. What fault model and coverage does the electrical test use? Node coverage is not fault coverage. Who owns the yield data, and will you see it? Ask for the first-pass yield trend and the top defect Pareto. What happens to a failed board? Repair, retest and disposition should be defined before the first board fails. What is the fixture strategy across NPI? Confirm flying probe at EVT/DVT and the plan to cut an ICT fixture at PVT. How Nex-G sizes a test plan Nex-G is an EMS and CNC shop in Hengli, Dongguan — 6,800 m², 100+ people, operating since 2006 (Zhuohang) — and the test plan is sized to risk, not to budget. The starting point is the same three gates every NPI passes through: EVT proves the design works, DVT proves it works at the edges of spec and environment, and PVT proves it can be built repeatedly. Test grows with the gates — flying probe and a bench functional test at EVT, a fuller electrical and X-ray plan at DVT, and a fixtured, documented, yield-tracked plan at PVT. The three gates, in detail. There is no minimum order: MOQ is one piece, and the shop handles a single prototype and a 10,000-unit run under the same quality system. Lead time scales with the work — roughly three days for a simple fast turn, seven for a standard build, and up to thirty for a complex board with many steps or surface finishes — but the test discipline does not scale down with the quantity. Quality is documented under ISO 9001 (certificate 116024/A/0001/UK/En), IATF 16949 (131941/A/0001/SM/En, which excludes product design under clause 8.3 — we manufacture, we do not take design responsibility) and ISO 14001 (116024/B/0001/UK/En), all issued through URS and current into 2027. For automotive programs the same system runs APQP and PPAP — process flow, control plan, PFMEA and SPC evidence — so a test plan is not a one-off but a documented, auditable part of the launch. Frequently asked questions What is the difference between ICT and flying probe?ICT uses a fixed bed-of-nails fixture and is fast and thorough but needs a costly fixture; flying probe uses moving probes, needs no fixture, and suits prototypes and low volume at the cost of slower throughput. Do I need X-ray inspection?If your board has BGAs, QFNs or other bottom-terminated packages, yes — those joints are invisible to optical inspection and X-ray is the only way to verify them. What is functional test?FCT powers and exercises the board as the end product would be used, catching defects that pass every other test. It is the most valuable check because it answers whether the board actually works. Can you test a prototype board?Yes — flying probe and functional test are the right tools for prototypes, because they need no fixture and adapt as the design changes. How much does PCBA test add to cost?It scales with the method: AOI is nearly free inline; ICT adds fixture cost amortized over volume; X-ray and FCT add per-board time. On a mature high-volume board, test is a small fraction of unit cost; on a prototype it is mostly setup. Do you do testing in-house?Yes — AOI, X-ray, ICT/flying probe and functional test under one quality system, so test results feed directly back into the build rather than bouncing between vendors. What is boundary scan, and when is it useful?Boundary scan (IEEE 1149.1) drives and reads the pins of compliant devices through a test access port, verifying interconnects without physical probe access. It is useful on dense boards and BGAs where a fixture cannot reach, and it complements — not replaces — ICT and AOI. What is the difference between node coverage and fault coverage?Node coverage is the fraction of nets a test touches; fault coverage is the fraction of realistic faults — shorts, opens, wrong value, missing part — the test would actually catch. Always ask which number is being quoted, and what fault model sits behind it. Do you have a minimum order quantity?No — MOQ is one piece. A single prototype and a production run go through the same quality system and the same test discipline. What certifications does the factory hold?ISO 9001, IATF 16949 (excluding product design under clause 8.3) and ISO 14001, issued through URS and current into 2027. A test strategy by product type The right test plan scales with risk, not with budget: ProductMinimum test plan Simple consumerAOI + basic FCT Connected / poweredAOI + ICT or flying probe + FCT With BGAs / QFNsAOI + X-ray + FCT Automotive / medicalFull ICT + X-ray + FCT + burn-in, with yield data Match the plan to the consequence of failure. A toy remote needs less than a brake controller — but both need a real functional test, not a power-on light. The full test guide. Not sure your board is testable?Send the design to [email protected] — we will flag the test-point gaps and propose a test plan sized to your risk, not your budget.Request a quote Related articlesSMT Assembly Step by StepPCB Assembly in China: How to Vet an EMS PartnerEVT → DVT → PVT: The Three Gates